Flash memory devices may typically be categorized as NOR-type or NAND-type based on the way that memory cells are connected. NOR-type flash memory devices may be further categorized as stacked-gate NOR-type or split-gate NOR-type based on the structure of the memory cell. A conventional split-gate NOR-type flash memory device is typically configured such that sources of a plurality of split-gate memory cells are commonly connected to one source line. As a result, a voltage drop on the source line depends on the number of memory cells that are programmed during a program operation. This may result in variations in the program voltage to be used in programming the memory cells.
FIG. 1 is a block diagram that illustrates a conventional split-gate NOR-type flash memory device. The split-gate NOR-type flash memory device of FIG. 1 includes a memory cell array 10, a row decoder 12, a word line driver 14, a source decoder 16, a source line driver 18, a column decoder and multiplexer 20, and a data input circuit 22. In FIG. 1, i number of bit lines are represented by one bit line.
As shown in FIG. 1, the memory cell array 10 includes (2m×ni) split-gate memory cells, which are connected between ni bit lines BL11 to BL1i, . . . , BLn1 to BLni, 2m word lines WL to WL2m, and m source lines SL1 to SLm. The ni bit lines are configured in n groups with each group including i bit lines. In two memory cells vertically adjacent to each other, sources are commonly connected to the source line, drains are connected to the same bit line, and gates are connected to corresponding respective word lines.
Operation of the split-gate NOR-type flash memory device of FIG. 1 will now be described. An erase operation in the memory cell array 10 is performed in such a way that a relatively high voltage VPP is applied to the word lines WL1 to WL2m and a ground or reference voltage is applied to the bit lines BL11 to BL1i, . . . , BLn1 to BLni. In a program operation, a relatively high voltage VPP is applied to a selected source line of the source lines SL1 to SLm, a ground or reference voltage is applied to non-selected source lines, a predetermined voltage is applied to a selected word line of the word lines WL1 to WL2m, and a ground or reference voltage is applied to non-selected word lines. A corresponding memory cell is programmed when a predetermined voltage is applied to the bit lines BL11 to BL1i, . . . , BLn1 to BLni, and a corresponding memory cell is not programmed when a power supply voltage is applied to those bit lines.
In a read operation, a ground or reference voltage is applied to the source lines SL1 to SLm, a power supply voltage is applied to a selected word line of the word lines WL1 to WL2m, a ground or reference voltage is applied to non-selected word lines, a predetermined voltage is applied to a selected bit line of the bit lines BL11 to BL1i, . . . , BLn1 to BLni, and a ground or reference voltage is applied to non-selected bit lines, so that data is read from a corresponding memory cell. In a standby condition, a ground or reference voltage is applied to the source lines SL1 to SLm, the word lines WL1 to WL2m, and the bit lines BL11 to BL1i, . . . , BLn1 to BLni. The row decoder 12 decodes an x-bit row address RA1 to RAx to generate the word line selection signals W1 to W2m. The word line driver 14 applies a relatively high voltage to the word lines WL1 to WL2m in response to the word line selection signals W1 to W2m in an erase operation. The word line driver 14 applies a predetermined voltage to a selected word line and applies a ground or reference voltage to non-selected word lines in a program operation. The word line driver 14 applies a power supply voltage to a selected word line and applies a ground or reference voltage to non-selected word lines in a read operation. The word line driver 14 applies a ground or reference voltage to the word lines WL1 to WL2m in a standby condition. The source decoder 16 decodes the row address RA1 to RA(x−1) (excluding the lowest bit of the row address RA1 to RAx) to generate m source line selecting signals S1 to Sm. The source line driver 18 drives the source lines SL1 to SLm in response to the m source line selection signals S1 to Sm. The source line driver 18 applies a ground or reference voltage to the source lines SL1 to SLm in an erase operation, applies a relatively high voltage to a selected source line of the source lines SL1 to SLm, applies a ground or reference voltage to non-selected source lines in a program operation, and applies a ground or reference voltage to the source lines SL1 to SLm in a read operation and a standby condition.
The column decoder and multiplexer 20 decodes a y-bit column address CA1 to CAy to generate i column selection signals and transmits data from n data input/output lines IO1 to IOn to n bit lines in response to the i column selection signals. That is, the column decoder and multiplexer 20 selects one bit line from among i bit lines for each of n groups of bit lines B11 to BL1i, . . . , BLn1 to BLni to transmit data from the n data input/output lines IO1 to IOn to the n bit lines. The column decoder and multiplexer 20 applies a ground or reference voltage to the bit lines B11 to BL1i, . . . , BLn1 to BLni in an erase operation, applies a predetermined voltage and/or a power supply voltage to selected bit lines from among the i bit lines for each of the n groups of bit lines BL11 to BL1i, . . . , BLn1 to BLni in a program operation, applies a predetermined voltage and/or a ground/reference voltage to selected bit lines from among the i bit lines for each of the n groups of bit lines BL11 to BL1i, . . . , BLn1 to BLni in a read operation, and applies a ground or reference voltage to the n groups of bit lines BL11 to BL1i, . . . , BLn1 to BLni in a standby condition. In a program operation, the data input circuit 22 transmits a power supply voltage level to corresponding data input/output lines when input data has a “high” logic level and transmits a predetermined voltage, which is responsive to a bias voltage VBIAS, to corresponding data input/output lines when input data has a “low” logic level.
Erase operations and program operations of the flash memory device of FIG. 1 will now be described. When an erase command is applied, the word line driver 14 applies a high voltage VPP to the word lines WL1 to WL2m, the source line driver 18 applies ground or reference voltage signals to the source lines SL1 to SLm, and the column decoder and multiplexer 20 applies a ground or reference voltage signal to the n groups of bit lines BL11 to BL1I, . . . , BLn1 to BLni. As a result, an erase operation for the memory cells in the memory cell array 10 is performed.
To illustrate a program operation, assume that a program command is applied, data DIN1 is at a “low” logic level, data DIN2 to DINn are at a “high” logic level, and the row address RA1 to RAx and the column address CA1 to CAy each have values of “00 . . . 0.”
The row decoder 12 decodes the row address RA1 to RAx to enable the word line selection signal W1. The source decoder 16 decodes the row address RA1 to RA(x−1) to enable the source line selection signal S1. The data input circuit 22 drives the input data DIN1 to a “low” logic level and the input data DIN2 to DINn to a “high” logic level to transmit a predetermined voltage or a power supply voltage to the data input/output lines IO1 to IOn. The word line driver 14 applies a predetermined voltage (typically about 1 volt) to the word line W1 in response to the word line selection signal W1 and applies a ground or reference voltage to the rest of the word lines WL2 to WL2m. The source line driver 18 applies a relatively high voltage VPP to the source line SL1 and applies a ground or reference voltage to the rest of the source lines SL2 to SLm. The column decoder and multiplexer 20 decodes the column address CA1 to CAy to select the first n bit lines BL11 to BLn1 of the n groups of bit lines BL11 to BL1I, . . . , BLn1 to BLni, applies a predetermined voltage (typically about 0.4 to 0.5 volts) to the bit line BL11 in response to a signal on the data input/output lines IO1 to IOn, and applies a power supply voltage level signal to the bit lines BL2I to BLn1. In this manner, the memory cells connected between the n bit lines BL11 to BLn1 and the word line WL1 are programmed. That is, the memory cell connected between the bit line BL11 and the word line WL1 is programmed because electric current flows from the source line SL1 to the bit line BL11, and the rest of the memory cells connected between the bit line BL11 and the word line WL1 are not programmed because electric current does not flow from the source line SL1 to the bit lines BL21 to BLn1.
The memory cells in the memory cell array may be programmed using the above-described method. Because one memory cell is programmed, a voltage drop that occurs on the source line SL1 may not be large. When input data DIN1 to DINn are applied at a “low” logic level, however, because all of the n memory cells connected to the source line SL1 are programmed, an electric current flows from the source line SL1 to the bit lines BL11, BL21, . . . , BLn1, which may result in a relatively large voltage drop on the source, line.
In other words, a conventional flash memory device may experience a larger voltage drop on the source line as the number of memory cells to be programmed increases. This may result in variations in the voltage used to program memory cells as the voltage drop on the source line varies.